EPF6016TC144-2N

 Provides an ideal low-cost, programmable alternative to highvolume gate array applications and allows fast design changes 

during prototyping or design testing

 Product features

– Register-rich, look-up table- (LUT-) based architecture

– OptiFLEX®

 architecture that increases device area efficiency

– Typical gates ranging from 5,000 to 24,000 gates (see Table1)

– Built-in low-skew clock distribution tree

– 100% functional testing of all devices; test vectors or scan chains 

are not required

 System-level features

– In-circuit reconfigurability (ICR) via external configuration 

device or intelligent controller

– 5.0-V devices are fully compliant with peripheral component 

interconnect Special Interest Group (PCI SIG) PCI Local Bus 

Specification, Revision 2.2

– Built-in Joint Test Action Group (JTAG) boundary-scan test 

(BST) circuitry compliant with IEEE Std. 1149.1-1990, available 

without consuming additional device logic

– MultiVolt

TM

 I/O interface operation, allowing a device to bridge 

between systems operating at different voltages

– Low power consumption (typical specification less than 0.5 mA 

in standby mode) 

– 3.3-V devices support hot-socketing

 

 

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